B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
A new efficient method for substrate-aware device-level placement (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Substrate noise modeling in early floorplanning of MS-SOCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or B* -tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.