DAC '96 Proceedings of the 33rd annual Design Automation Conference
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Modeling and simulation of the interference due to digital switching in mixed-signal ICs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Substrate noise: analysis and optimization for IC design
Substrate noise: analysis and optimization for IC design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Substrate noise modeling in early floorplanning of MS-SOCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SWAN: high-level simulation methodology for digital substrate noise generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method for switching activity analysis of VHDL-RTL combinatorial circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Currents injected by CMOS digital circuit blocks into the powergrid and into the substrate of a system-on-a-chip may affect reliabilityand performance of other sensitive circuit blocks. To verify thecorrect operation of the system, an upper bound for the spectrum ofthe noise current has to be provided with respect to all possible transitionsof the circuit inputs. The number of input transitions is exponentialin the number of circuit inputs. In this paper, we present anovel approach for the computation of the upper bound that avoidsthe untractable exhaustive exploration of the entire space. Its computationalcomplexity is indeed linear in the number of gates. Ourapproach requires CMOS standard cell libraries to be characterizedfor injected noise current. In this paper, we also present an approachfor this characterization of CMOS standard cells. Experimental resultshave proven the accuracy of both the algorithm and the noisecurrent models used for the library characterization.