A method for switching activity analysis of VHDL-RTL combinatorial circuits

Authors:
Felipe Machado;Teresa Riesgo;Yago Torroja
Affiliations:
División de Ingeniería Electrónica, Universidad Politécnica de Madrid, E.T.S.I. Industriales, Madrid, Spain;División de Ingeniería Electrónica, Universidad Politécnica de Madrid, E.T.S.I. Industriales, Madrid, Spain;División de Ingeniería Electrónica, Universidad Politécnica de Madrid, E.T.S.I. Industriales, Madrid, Spain
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.