Minimal energy asynchronous dynamic adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
The design of a dataflow coprocessor for low power embedded hierarchical processing
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A method for switching activity analysis of VHDL-RTL combinatorial circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Designing CMOS Circuits for Low Power provides the fundamentals of low power design for logic, circuit, and physical design level as well as the "design story" of two innovative low power systems developed in the context of European Low Power Initiative for Electronic System Design. The main objective is to present in-depth analytical and design capabilities for low power design CMOS circuits.