The design of a dataflow coprocessor for low power embedded hierarchical processing

Authors:
Yijun Liu;Steve Furber;Zhenkun Li
Affiliations:
The Sensor Network Group, The Faculty of Computer, Guangdong University of Technology, Guangzhou, China;The Advanced Processor Technologies Group, The School of Computer Science, The University of Manchester, Manchester, UK;The Sensor Network Group, The Faculty of Computer, Guangdong University of Technology, Guangzhou, China
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

Power consumption has become one of the most important concerns in the design of embedded processor; the power dissipation of microprocessors grows rapidly as the development of CMOS technology packs more transistors per unit area. However, the potential for further power saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative approach to save power is proposed in this paper — embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments, such as small loops, function calls and long equation evaluations, very efficiently. We demonstrate a factor of 7 improvement in power-efficiency over current general-purpose processors. Dataflow techniques are not new, but we apply the concept to address a new problem — to improve the power-efficiency of conventional processors.