ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A bitmap scaling and rotation design for SH1 low power CPU
MSWiM '99 Proceedings of the 2nd ACM international workshop on Modeling, analysis and simulation of wireless and mobile systems
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Embedded Computing Systems (TECS)
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Tiny instruction caches for low power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Decomposition of Instruction Decoder for Low Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Scheduling Reusable Instructions for Power Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 1
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction
Proceedings of the 2004 international symposium on Low power electronics and design
Instruction buffering exploration for low energy VLIWs with instruction clusters
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
Instruction buffering exploration for low energy embedded processors
Journal of Embedded Computing - Low-power Embedded Systems
Iterative compilation for energy reduction
Journal of Embedded Computing - Cache exploitation in embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power embedded DSP core for communication systems
EURASIP Journal on Applied Signal Processing
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Enabling large decoded instruction loop caching for energy-aware embedded processors
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Instruction buffering for nested loops in low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy reduction scheduling mechanism for a high-performance soc architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Embedded Systems Design
The design of a dataflow coprocessor for low power embedded hierarchical processing
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Asynchronous functional coupling for low power sensor network processors
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems
International Journal of Handheld Computing Research
Towards a performance- and energy-efficient data filter cache
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Journal of Signal Processing Systems
DLIC: Decoded loop instructions caching for energy-aware embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
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Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8/spl times/8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%.