Instruction buffering for nested loops in low-power design

Authors:
ChiTa Wu;Ang-Chih Hsieh;Ting Ting Hwang
Affiliations:
Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan, R.O.C;Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan, R.O.C;Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan, R.O.C
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

Several loop-buffering techniques were proposed for reducing power consumption of embedded processors. Although the schemes are effective in reducing power, they work for unnested loops (or the inner-most loop in nested loops) only. In this paper, we propose a stack-based controller which can handle sequential loops being nested in a loop of all styles and the if-then-else construct inside of a loop. Our experiments by power estimator Wattch show that the reduction in energy consumption using our technique is up to 36% improvement of the design without buffering technique and has 25% more improvement when compared to the results which handle inner-most loop only at the fetch and decode stages.