Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new efficient method for substrate-aware device-level placement (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Substrate noise: analysis and optimization for IC design
Substrate noise: analysis and optimization for IC design
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of Mixed-Signal System-on-Chips (MS-SOCs). We assume no precise layout information about IP cores is available. We also propose an empirical formula for separation-dependent coupling between large-area noisy ports and small-area sensitive ports for lightly-doped substrates that are preferred for mixed-signal circuits. The interaction between digital and analog blocks is incorporated into our floorplanner, which reduces the overall noise and the number of analog blocks with noise limit violations. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.