Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Effects of simultaneous switching noise on the tapered buffer design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing the VCO jitter due to the digital simultaneous switching noise
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Substrate noise modeling in early floorplanning of MS-SOCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analysis of the impact of bus implemented EDCs on on-chip SSN
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Charge recycling in MTCMOS circuits: concept and analysis
Proceedings of the 43rd annual Design Automation Conference
Minimizing peak power in synchronous logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Optimizing selective decoupling capacitors by genetic algorithm for multiplayer power bus
ISTASC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel design for evaluating simultaneous switching noise within an enhanced IBIS model
WSEAS Transactions on Circuits and Systems
Ground-bouncing-noise-aware combinational MTCMOS circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A new current-mode fast-transient-response shunt regulator using CMOS technology
Analog Integrated Circuits and Signal Processing
Ground bouncing noise suppression techniques for data preserving sequential MTCMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards process variation-aware power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reactivation noise suppression with sleep signal slew rate modulation in MTCMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.