Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Coarse-grain MTCMOS sleep transistor sizing using delay budgeting
Proceedings of the conference on Design, automation and test in Europe
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Worst case power/ground noise estimation using an equivalent transition time for resonance
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Proceedings of the 2009 International Conference on Computer-Aided Design
Sleep transistor sizing for leakage power minimization considering charge balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that the proposed design is able to track process variation such that the surge current and the wakeup time are both kept to expectation in all process corners.