Analysis of glitch power dissipation in CMOS ICs
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
di/dt Noise in CMOS Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Decreased effectiveness of on-chip decoupling capacitance in high-frequency operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-Aware Power-Noise Reduction in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Distributed power network co-design with on-chip power supplies and decoupling capacitors
Proceedings of the System Level Interconnect Prediction Workshop
Towards process variation-aware power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr ≤ 2√LgCd. Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ≥ 2√LgCd. The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ≅ 2√LgCd, referred to as the equivalent transition time for resonance.