On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Power distribution paths in 3-D ICS
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Worst case power/ground noise estimation using an equivalent transition time for resonance
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
A digitally-calibrated phase-locked loop with supply sensitivity suppression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Distributed power network co-design with on-chip power supplies and decoupling capacitors
Proceedings of the System Level Interconnect Prediction Workshop
Proceedings of the Conference on Design, Automation and Test in Europe
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Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard ceil circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.