A digitally-calibrated phase-locked loop with supply sensitivity suppression

Authors:
Shih-Yuan Kao;Shen-Iuan Liu
Affiliations:
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

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Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ICs

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Abstract

A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional opposite-supply-sensitivity pair is digitally calibrated to suppress the supply voltage sensitivity. The circuit is fabricated in a 0.18-µm CMOS technology and the core area occupies 0.235 mm2. The total power consumption is 16.2 mW for a supply voltage of 1.8 V and an operating frequency of 1.5 GHz. For a 100 m Vpp, 110 kHz sinusoidal waveform noise applied to the supply, the measured rms jitters without and with calibration are 16.5 and 9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL achieves the rms jitter improvement by a factor of 41.2% under the proposed digitally-calibrated technique.