Worst case power/ground noise estimation using an equivalent transition time for resonance
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
A novel design for evaluating simultaneous switching noise within an enhanced IBIS model
WSEAS Transactions on Circuits and Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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With high integration density of today's electronic system and reduced noise margins, maintaining high power integrity becomes more challenging for high performance design. Inserting decoupling capacitors is one important and effective solution to improve the power integrity. The existing decoupling capacitor optimization approaches meet constraints on input impedance. In this paper, we show that impedance metric leads to large overdesign and then develop a noise-driven optimization algorithm for decoupling capacitors in packages for power integrity. We use the simulated annealing algorithm to minimize the total cost of decoupling capacitors under the constraints of a worst case noise bound. The key enabler for efficient optimization is an incremental worst case noise computation based on fast Fourier transform over incremental impedance matrix evaluation. Compared to the existing impedance-based approaches, our algorithm reduces the decoupling capacitor cost by 3times and is also more than 10times faster even with explicit noise computation