Practical methods of optimization; (2nd ed.)
Practical methods of optimization; (2nd ed.)
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Timing Correction and Optimization with Adaptive Delay Sequential Elements
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Peak current reduction by simultaneous state replication and re-encoding
Proceedings of the International Conference on Computer-Aided Design
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Minimizing peak power decreases the probability of failure due to hot carrier effects and electromigration. It also reduces the maximum IR voltage drop, the magnitude of substrate noise, and packaging costs. In mobile applications, minimizing peak power can help reduce the battery size. In synchronous circuits the peak power draw is correlated with clock transitions when the entire clock distribution network, all of the flip-flops and their immediate fanout switch simultaneously. In this paper, we propose an efficient, deterministic method for finding the optimal distribution of clock latencies for minimizing peak power consumption. Our algorithm spreads the clock transitions using timing slacks on non-critical paths and preserves the circuit performance. We validate our method by transistor level simulations on benchmark circuits. These experiments show that our method can reduce the peak power consumption up to 55 percent in circuits whose peak power is due to simultaneous clock transitions.