Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Minimizing peak power in synchronous logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
State re-encoding for peak current minimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IR Drop Reduction via a Flip-Flop Resynthesis Technique
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Peak current is one of the important considerations for circuit design and testing in the deep sub-micron technology. In a synchronous finite state machine (FSM), it is observed that the peak current happens at the moment of state transitions and it has a strong correlation with the maximum number of state registers switching in the same direction simultaneously [2], which we refer to as the peak switching value (PSV). We propose a FSM synthesis method to reduce PSV by seamlessly combining state replication and state re-encoding techniques. Our experiments show that out of 52 FSM benchmarks encoded by a state-of-the-art power-driven encoding algorithm POW3 [1], 36 of them are not optimal in terms of PSV. Our approach can improve on 34 of them with an average 39.2% PSV reduction, while the only comparable PSV-driven FSM synthesis technique [2] can improve on 27 benchmarks with an average 24.5% reduction. Furthermore, we compare our approach with [2] after the FSMs are implemented using an industry EDA tool. The results show that our approach reduces the peak current in the circuits by 13% on average and the total power by 3% with a mere 2% overhead in area.