Timing Correction and Optimization with Adaptive Delay Sequential Elements

Authors:
Kambiz Rahimi;Seth Bridges;Chris Diorio
Affiliations:
-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Year:
2004

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Abstract

This paper introduces Adaptive Delay Sequential Elements (ADSEs). ADSEs are registers that use nonvolatile, floating-gate transistors to tune their internal clock delays. We propose ADSEs for correcting timing violations and optimizing circuit performance. We present an ADSE circuit example, system architecture, and tuning methodology. We present experimental results that demonstrate the correct operation of our example circuit and discuss the die-area impact of using ADSEs. Our experiments also show that voltage and temperature sensitivity ofADSEs are comparable to non-adaptive flip-flops.