Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Ground-bouncing-noise-aware combinational MTCMOS circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Advanced variance reduction and sampling techniques for efficient statistical timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ground bouncing noise suppression techniques for data preserving sequential MTCMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to 183.1× as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.