Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Switching Codes for Delta-I Noise Reduction
IEEE Transactions on Computers
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Coding Techniques for Low Switching Noise in Fault Tolerant Busses
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
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In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN is impacted by different bus transitions, pointing out its dependency on the number and placement of switching wires. Afterwards, we present an analytical model that we have developed in order to estimate the SSN, and that we prove to be very accurate in SSN prediction. Finally, by employing the developed model, we estimate the SSN due to different EDCs implemented on an on-chip bus. In particular, we highlight how their differences in the number of switching wires, bus parallelism and codewords influence the on-chip SSN.