Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Vector generation for power supply noise estimation and verification of deep submicron designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Principles of substrate crosstalk generation in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of the impact of bus implemented EDCs on on-chip SSN
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe
Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology
Analog Integrated Circuits and Signal Processing
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dI/dt and dV/dt noise generation and propagation mechanisms.