Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fast computation of discharge current upper bounds for clustered power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and estimation of power supply noise using linear programming
Proceedings of the International Conference on Computer-Aided Design
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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This paper presents new techniques for generating a small set of patterns for power network simulation to estimate the maximum power supply noise of the chip, as well as to identify cells/blocks for which the power supply noise at their V/sub dd/ ports exceeds a specified threshold. We first present an efficient, cell-level simulator for estimating power supply noise of any given vectors. Based on this simulator, we then apply the genetic algorithm (GA) to derive a small set of patterns producing high power supply noise. To identify critical nodes with power supply noise exceeding a threshold, the multiobjective GA is adapted for pattern generation. To achieve high coverage of such critical nodes, we model the search criteria as the maximum weighted matching of a bipartite graph, and guide the search direction according to the matching results. The derived patterns will be simulated on a power network simulator to obtain a lower bound of the maximum power supply noise and to identify the critical nodes. Experimental results on public benchmark circuits, as well as some industrial designs, are presented to demonstrate the efficiency and effectiveness of the proposed approaches.