Analysis of the impact of bus implemented EDCs on on-chip SSN
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Crosstalk- and SEU-Aware Networks on Chips
IEEE Design & Test
Parallel processing for block ciphers on a fault tolerant networked processor array
International Journal of High Performance Systems Architecture
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As device geometries shrink, power supply voltage decreases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming crucial in determining the signal integrity of a system. In this paper we propose new ways of merging transition reducing coding techniques with coding techniques for fault tolerant busses (implementing either error detecting codes and error recovery, or correcting codes). In particular, we focus on merging bus-invert code along with the employed error detection or correction coding technique, and show that the maximum number of simultaneous switching drivers can be drastically reduced, thus reducing the SSN and increasing signal integrity. Furthermore, we show how, by properly merging the bus invert encoder and the check bit generator, the latency introduced by the proposed coding techniques can be minimized and the number of additional wires can be kept minimal.