Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Coding Techniques for Low Switching Noise in Fault Tolerant Busses
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Early, Accurate Dependability Analysis of CAN-Based Networked Systems
IEEE Design & Test
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Exploiting ECC Redundancy to Minimize Crosstalk Impact
IEEE Design & Test
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Device and architecture concurrent optimization for FPGA transient soft error rate
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
| Hi-index | 0.00 |
As the complexity of designs increases and the technology scales down into the deep sub-micron domain, devices and interconnections are subject to new types of malfunctions and failures. This work intends to evaluate the effect of Single Event Upsets (SEUs) and crosstalk faults in a Network-on-Chip switch by performing fault injection simulations, allowing an accurate analysis of the impact of these faults over the switch service. The results show that such faults might affect the switch behavior, with errors ranging from simple loss of packets up to the permanent interruption of the switch service.