Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Proceedings of the 43rd annual Design Automation Conference
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
New heuristic algorithms for low-energy mapping and routing in 3D NoC
International Journal of Computer Applications in Technology
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In this paper, we discuss the possibility of achieving on-chip fault-tolerant communication based on a newcommunication paradigm called stochasticcommunication.Specifically, for a generic tile-basedarchitecture, we present a randomized algorithm whichnot only separates computation from communication, butalso provides the required fault-tolerance to on-chipfailures.This new technique is easy and cheap toimplement in SoCs that integrate a large number ofcommunicating IP cores.