TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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In this paper, the problem of bus driven floor-planning is addressed. Given a set of modules and bus specifications, a floorplain solution including the bus routes will be generated with the floorplan area and total bus area minimized. Some previous works have addressed this problem with restricted bus shapes of 0-bend, 1-bend or 2-bend [1]. However, in this paper, we address this bus driven floorplanning without any limitations on the shapes of the buses. We solve this problem by a simulated annealing based floorplanner using the Transitive Closure Graph (TCG) representation [6]. Experimental results show that we can improve over [1] significantly in terms of both run time and quality, since there are more flexibilities in routing the buses and complex shape validataion steps are not needed. For data sets with buses connecting a large number of blocks, our approach can still generate high quality solutions effectively, while the approach [1] of restricting to 2-bend buses often cannot give any feasible solutions.