Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design

Authors:
De-Yu Liu;Wai-Kei Mak;Ting-Chi Wang
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan Roc;National Tsing Hua University, Hsinchu, Taiwan Roc;National Tsing Hua University, Hsinchu, Taiwan Roc
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

Citing 9
Cited 0

Multilevel hypergraph partitioning: application in VLSI domain

DAC '97 Proceedings of the 34th annual Design Automation Conference
Temperature-aware microarchitecture

Proceedings of the 30th annual international symposium on Computer architecture
Modern floorplanning based on fast simulated annealing

Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Integrating dynamic thermal via planning with 3D floorplanning algorithm

Proceedings of the 2006 international symposium on Physical design
3D floorplanning with thermal vias

Proceedings of the conference on Design, automation and test in Europe: Proceedings
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pad assignment for die-stacking System-in-Package design

Proceedings of the 2009 International Conference on Computer-Aided Design
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we study a floorplanning problem for die-stacking System-in-Package (SiP) design in which the wire bonding method is used to connect signals between different dies. We present an approach which sequentially determines a floorplan for each die such that the generated floorplan has minimal on-chip wirelength and satisfies given fixed-outline and temperature constraints. The experimental results indicate that our approach has 100% successful rate in producing a feasible floorplan for each test case.