An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast evaluation of sequence pair in block placement by longest common subsequence computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modern floorplanning based on B*-tree and fast simulated annealing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
In this paper, we propose a stable fixed-outline floorplanning method(IARFP). An elaborated method for perturbing solutions, Insertion after Remove(IAR), is devised for the simulated annealing. The IAR operation uses the technique of enumerating positions in Sequence Pair and greatly accelerates the searching. Moreover, based on the analysis of diverse objective functions used in the existing researches, we suggest a new objective function, which is still effective when combined with other objectives, for the fixed-outline floorplanning. Compared with the previous fixed-outline floorplanners, the proposed method is effective and efficient. Experiments showed that the proposed fixed-outline floorplanner achieved 100% success rate efficiently when optimizing area and wire-length simultaneously, while getting much smaller wirelength. On the other hand, we validated once more by experiments that aspect ratio close to one is beneficial to wire-length.