Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy minimization using multiple supply voltages
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
Placement with Alignment and Performance Constraints Using the B*-Tree Representation
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Voltage island-driven floorplanning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
Postplacement voltage assignment under performance constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
Proceedings of the 2009 international symposium on Physical design
Voltage-island driven floorplanning considering level-shifter positions
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 ACM Symposium on Applied Computing
A revisit to voltage partitioning problem
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Power efficient voltage islanding for Systems-on-Chip from a floorplanning perspective
Proceedings of the Conference on Design, Automation and Test in Europe
Low power discrete voltage assignment under clock skew scheduling
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Postplacement Voltage Island Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
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Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints.