Post-placement voltage island generation under performance requirement

  • Authors:
  • Huaizhi Wu;I-Min Liu;M. D. F. Wong;Yusu Wang

  • Affiliations:
  • Cadence Design Syst., Inc., San Jose, CA, USA;Pennsylvania State Univ., University Park, PA, USA;California Univ., Santa Barbara, CA, USA;California Univ., Santa Barbara, CA, USA

  • Venue:
  • ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
  • Year:
  • 2005

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Abstract

High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer-grain power and performance trade-off. In this work we propose a methodology on top of a set of algorithms to exploit non-trivial voltage island boundaries for optimal power versus design cost trade-off under performance requirement. Our algorithms are efficient, robust and error-bounded, and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a ten-fold improvement of our method over current logical-boundary based industry approach.