Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-placement voltage island generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Stochastic thermal simulation considering spatial correlated within-die process variations
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, a grid-based multiple supply voltage (MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis (SSTA) to take into account the thermal effect on circuit timing, the statistical power_delay_sensitivity-slack product to be the optimization criterion, and an incremental update of statistical timing to save the runtime. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of the thermal effect in the circuit simulation is imperative.