A study of permutation crossover operators on the traveling salesman problem
Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application
LEneS: task scheduling for low-energy systems using variable supply voltage processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Visual assessment of a real-time system design: a case study on a CNC controller
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms
SOC'09 Proceedings of the 11th international conference on System-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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Voltage islands provide a very good opportunity for minimizing the energy consumption of core-based Networks-on-Chip (NoC) design by utilizing a unique supply voltage for the cores on each island. This paper addresses various complex design issues for NoC implementation with voltage islands. A novel design framework based on genetic algorithm is proposed to optimize both the computation and communication energy with the creation of voltage islands concurrently for the NoC using multiple supply voltages. The algorithm automatically performs tile mapping, routing path allocation, link speed assignment, voltage island partitioning and voltage assignment simultaneously. Experiments using both real-life and artificial benchmarks were performed and results show that, by using the proposed scheme, significant energy reduction is obtained.