Time and energy efficient mapping of embedded applications onto NoCs

Authors:
César Marcon;André Borin;Altamiro Susin;Luigi Carro;Flávio Wagner
Affiliations:
UFRGS, Porto Alegre, RS - Brazil;UFRGS, Porto Alegre, RS - Brazil;UFRGS, Porto Alegre, RS - Brazil;UFRGS, Porto Alegre, RS - Brazil;UFRGS, Porto Alegre, RS - Brazil
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 10
Cited 14

The turn model for adaptive routing

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Parallel computing (2nd ed.): theory and practice

Parallel computing (2nd ed.): theory and practice
TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers

Proceedings of the 39th annual Design Automation Conference
Power and performance evaluation of globally asynchronous locally synchronous processors

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes

ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Packetization and routing analysis of on-chip multiprocessor networks

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Energy-aware synthesis of networks-on-chip implemented with voltage islands

Proceedings of the 44th annual Design Automation Conference
Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms

RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A decentralised task mapping approach for homogeneous multiprocessor network-on-chips

International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms

Journal of Systems Architecture: the EUROMICRO Journal
An ILP formulation for task mapping and scheduling on multi-core architectures

Proceedings of the Conference on Design, Automation and Test in Europe
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs

Journal of Systems Architecture: the EUROMICRO Journal
CAFES: A framework for intrachip application modeling and communication architecture design

Journal of Parallel and Distributed Computing
A survey on application mapping strategies for Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
Mapping on multi/many-core systems: survey of current and emerging trends

Proceedings of the 50th Annual Design Automation Conference
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New heuristic algorithms for low-energy mapping and routing in 3D NoC

International Journal of Computer Applications in Technology
Congestion-aware scheduling for NoC-based reconfigurable systems

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

This work analyzes, the mapping of applications onto generic regular Networks-on-Chip (NoCs). Cores must be placed considering communication requirements so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus potential contentions in the intercommunication of the cores. Experimental results for a suite of 22 benchmarks and various NoC sizes show that a 42% average reduction in the execution time of the mapped application can be obtained, together with a 21% average reduction in the total energy consumption for state-of-the-art technologies.