Proceedings of the conference on Design, automation and test in Europe - Volume 1
Characterization of logic circuit techniques for high leakage CMOS technologies
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Leakage-aware intraprogram voltage scaling for embedded processors
Proceedings of the 43rd annual Design Automation Conference
Efficient and scalable compiler-directed energy optimization for realtime applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Efficient and scalable compiler-directed energy optimization for realtime applications
Proceedings of the conference on Design, automation and test in Europe
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy minimization for real-time systems with non-convex and discrete operation modes
Proceedings of the Conference on Design, Automation and Test in Europe
Low power asynchronous circuit back-end design flow
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, circuit design and micro-architectural changes are required. Consequently, to focus the optimization efforts in the right direction, the models proposed and studies performed in this work are a first step for understanding the relative importance of leakage and dynamic energy in future technologies. Further, we analyze the effectiveness of two energy reduction mechanisms that employ voltage scaling, namely, supply and threshold voltage selection. We consider the impact of imminent technology changes and packaging improvements while showing that neglecting the impact of temperature may lead to underestimate the power savings by up to 19.5%.