Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Collaborative Operating System and Compiler Power Management for Real-Time Applications
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Optimal Voltages and Sizing for Low Power
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
ACM Transactions on Architecture and Code Optimization (TACO)
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Efficient and scalable compiler-directed energy optimization for realtime applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient and scalable compiler-directed energy optimization for realtime applications
Proceedings of the conference on Design, automation and test in Europe
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Feedback-controlled reliability-aware power management for real-time embedded systems
Proceedings of the 45th annual Design Automation Conference
Dynamic voltage scaling of supply and body bias exploiting software runtime distribution
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on high-performance embedded architectures and compilers III
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With scaling of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Conventional dynamic voltage scaling (DVS) techniques fail to accurately address theimpact of scaling on system power consumption and hence, are incapable ofachieving energy efficient solutions. To overcome this problem, we utilizeadaptive body biasing (ABB) to adjust transistors' threshold voltage at runtime. We develop a leakage-aware compilation methodology that targets embedded processors with both DVS and ABBcapabilities. Our technique has the unique advantage of jointly optimizing active and leakage energy dissipation. Considering the delay and energy penalty of switching between operating modes of the processor and under deadline constraint, our compiler improves the energy consumption of the generated code by average of 13.07% and up to 30.26% at 90nm. While our technique's improvement in energy dissipation over conventional DVS is marginal (4.54%) at 130nm,the average improvement continues to grow to 7.8%, 15.94% and 29.56% for 90nm, 65nm and 45 technology nodes, respectively.