Scheduling precedence graphs in systems with interprocessor communication times
SIAM Journal on Computing
Proceedings of the 6th international workshop on Hardware/software codesign
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Improving dynamic voltage scaling algorithms with PACE
Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
Profile-based optimal intra-task voltage scheduling for hard real-time applications
Proceedings of the 41st annual Design Automation Conference
Exploiting Barriers to Optimize Power Consumption of CMPs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems
Proceedings of the 42nd annual Design Automation Conference
Optimizing intra-task voltage scheduling using data flow analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Leakage-aware intraprogram voltage scaling for embedded processors
Proceedings of the 43rd annual Design Automation Conference
Runtime distribution-aware dynamic voltage scaling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient and scalable compiler-directed energy optimization for realtime applications
Proceedings of the conference on Design, automation and test in Europe
Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time
Proceedings of the 44th annual Design Automation Conference
Slice-balancing H.264 video encoding for improved scalability of multicore decoding
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SFCS '94 Proceedings of the 35th Annual Symposium on Foundations of Computer Science
Dynamic voltage scaling of supply and body bias exploiting software runtime distribution
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal intratask dynamic voltage-scaling technique and its practical extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
| Hi-index | 0.03 |
Dynamic voltage and frequency scaling (DVFS) for a parallel software program is crucial for lowering the ever-increasing power consumption of multiprocessor systems-on-chips (SoCs). In this paper, we propose an analytical DVFS method that judiciously exploits slack by considering the varying parallelism over each path in a task graph. The proposed method overcomes the conventional pessimistic assumption on the remaining workload, i.e., worst-case execution cycle. It yields minimum average energy consumption by utilizing the runtime distribution of a software program while satisfying the deadline constraints. The proposed method tackles leakage power consumption as well as dynamic power consumption by combined Vdd/Vbb scaling. Compared to conventional method [15], experimental results show that the proposed method provides up to 49.20% energy reduction for a set of synthetic task graphs and yields 23.93% and 27.15% energy reductions for two multimedia applications, namely, the H.264 encoder and decoder, respectively.