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A Chip-Multiprocessor Architecture with Speculative Multithreading
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Piranha: a scalable architecture based on single-chip multiprocessing
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Parallel Computer Architecture: A Hardware/Software Approach
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IEEE Computational Science & Engineering
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
WOMPAT '01 Proceedings of the International Workshop on OpenMP Applications and Tools: OpenMP Shared Memory Parallel Programming
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
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Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
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The energy efficiency of CMP vs. SMT for multimedia workloads
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The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power through compiler-directed barrier synchronization elimination
Proceedings of the 2006 international symposium on Low power electronics and design
Online power-performance adaptation of multithreaded programs using hardware event-based prediction
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Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
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Low-complexity policies for energy-performance tradeoff in chip-multi-processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-optimal synchronization primitives for single-chip multi-processors
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable power control for many-core architectures running multi-threaded applications
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Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Criticality stacks: identifying critical threads in parallel programs using synchronization behavior
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Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.