The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Scheduling Computer and Manufacturing Processes
Scheduling Computer and Manufacturing Processes
ET2: a metric for time and energy efficiency of computation
Power aware computing
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
PACE: A New Approach to Dynamic Voltage Scaling
IEEE Transactions on Computers
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
Practical PACE for embedded systems
Proceedings of the 4th ACM international conference on Embedded software
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Best of Both Latency and Throughput
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Exploiting Barriers to Optimize Power Consumption of CMPs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Power and performance optimization at the system level
Proceedings of the 2nd conference on Computing frontiers
Scheduling for heterogeneous processors in server systems
Proceedings of the 2nd conference on Computing frontiers
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Minimizing expected energy in real-time embedded systems
Proceedings of the 5th ACM international conference on Embedded software
Environment-conscious scheduling of HPC applications on distributed Cloud-oriented data centers
Journal of Parallel and Distributed Computing
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Chip-multi-processor (CMP) utilize multiple energy-efficient processing elements (PEs) to deliver high performance while reducing energy-consumption. Dynamic frequency-Voltage Scaling (DVS) balances performance and energy consumption by varying PEs' frequency-voltage workpoints to save energy while meeting performance requirements. We consider multi-task CMP applications with unknown workloads, and dynamically set workpoints to minimize ET2. Heuristic policies for serial/parallel task-graphs are investigated. We compare these policies to a theoretical bound and show that they achieve good results with low complexity. In most cases the simplest policy, which usually assigns constant workpoints, is also the most cost-effective one.