New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only)

• Authors: Fred J. Pollack
• Venue: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
• Year: 1999

Over the last 15 years, CMOS scaling simplified the task of the microprocessor architect. With each new process technology, frequency increased by -50%, and transistor density increase by 100 percent. Also, the improvements in manufacturing technology (larger wafers and higher yields) allowed for increasing die sizes without increasing cost. Projections of die sizes of 1 square inch or higher were common.However, the end of these easy times is in sight, and several new challenges are facing the architect. Die size is no longer going to be limited by equipment or manufacturing cost, but rather by power. To date the approach has been to lower voltage with each process generation. But as voltage is lowered, leakage current and energy increase, contributing to higher power. And the problems extend beyond power dissipation to power delivery/distribution and increasing power density.This talk will first look at the historical trends of CMOS process technology in the context of past microprocessors. It will then look at the implications of continued CMOS scaling, as described above, and the new challenges they pose. Microarchitecture techniques that have exacerbated the power problem will also be covered. Finally, the talk will describe some of the microarchitecture directions that may lead to more power-efficient and cost-efficient microprocessors.