Lowering power consumption in clock by using globally asynchronous locally synchronous design style

System-level power optimization: techniques and tools

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power and performance evaluation of globally asynchronous locally synchronous processors

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture

Automatic Production of Globally Asynchronous Locally Synchronous Systems

EMSOFT '02 Proceedings of the Second International Conference on Embedded Software

Optimal buffered routing path constructions for single and multiple clock domain systems

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Throughput-driven IC communication fabric synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

System-Level Point-to-Point Communication Synthesis Using Floorplanning Information

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Clocking strategies for networks-on-chip

Networks on chip

Optimal partitioning of globally asychronous locally synchronous processor arrays

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Application adaptive energy efficient clustered architectures

Proceedings of the 2004 international symposium on Low power electronics and design

ParIS: a parameterizable interconnect switch for networks-on-chip

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

A switch architecture and signal synchronization for GALS system-on-chips

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Multi-objective mapping for mesh-based NoC architectures

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Exploiting Barriers to Optimize Power Consumption of CMPs

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks

IEEE Transactions on Computers

Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture

Proceedings of the 2006 international symposium on Low power electronics and design

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Asynchronous arbiter for micro-threaded chip multiprocessors

Journal of Systems Architecture: the EUROMICRO Journal

Design of rotary clock based circuits

Proceedings of the 44th annual Design Automation Conference

A predictive NoC architecture for vision systems dedicated to image analysis

EURASIP Journal on Embedded Systems

System-level throughput analysis for process variation aware multiple voltage-frequency island designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low-power rotary clock array design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A flexible communication scheme for rationally-related clock frequencies

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design

Distributed DVFS using rationally-related frequencies and discrete voltage levels

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

A low latency wormhole router for asynchronous on-chip networks

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

GALDS: a complete framework for designing multiclock ASICs and socs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems

Exploring pausible clocking based GALS design for 40-nm system integration

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

A fast, source-synchronous ring-based network-on-chip design

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe