A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
Digital Technical Journal
Digital systems engineering
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
A switch architecture and signal synchronization for GALS system-on-chips
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
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One of the main problems when designing today's ASICs, is to distribute a skew-free synchronous clock over the whole chip. A large part of the power is also consumed in the clock-tree, in some cases as much as 50% of the total power consumption of the chip, because the large wires in the clock-tree are switched often. To attack these two problems, several methods have been discussed in the research literature over the years, from the more obvious solution of using asynchronous communication between locally clocked regions (Globally Asynchronous Locally Synchronous - GALS) to more fancy methods like distributing a standing wave on the clock-wires across the whole chip. In this chapter, we go through different clocking methods that has been proposed over the years and are suitable for the NoC scheme as well as presenting a new and clever way of distributing a Quasi-synchronous, i.e., a perfectly synchronous, but not skew-less, clock across an entire NoC-chip.