Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Introduction to VLSI Systems
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Communication Architectures for System-on-Chip
Proceedings of the 14th symposium on Integrated circuits and systems design
Clocking strategies for networks-on-chip
Networks on chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A methodology for design of unbuffered router microarchitecture for S-mesh NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Increasing power consumption and growing design effort are considered limiting factors in the design of chip-wide synchronous System-on-Chip designs. The attempt to get over these problems leads to an intensified look at asynchronous communication solutions, sometimes based on Network-on-Chips. Despite this basically asynchronous approach, most of the actual research work is not supporting a globally genuinely-asynchronous solution. We present a modular switch for a true globally asynchronous interconnect network. Independent clock generators in each switch maintain a local clock thus avoiding a global clock at the level of the interconnect network. The general switch architecture is described and the integration of the synchronization technique used to resolve metastability is discussed in detail. First synthesis results of a prototypical VLSI implementation are presented.