A methodology for design of unbuffered router microarchitecture for S-mesh NoC

Authors:
Hao Liu;Feifei Cao;Dongsheng Liu;Xuecheng Zou;Zhigang Zhang
Affiliations:
Henan Electric Power Research Institute, Zhengzhou, China and Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan, China;Henan Electric Power Industrial School, Zhengzhou, China;Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan, China;Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan, China;Henan Electric Power Research Institute, Zhengzhou, China
Venue:
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Year:
2010

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Abstract

Currently, most of Network on-Chip (NoC) architectures have some limitation in routing decisions. And it makes router nodes overloaded, and sequentially forms deadlock, livelock and congestion. A simple unbuffered router microarchitecture for S-mesh NoC architecture is proposed in this paper. Unbuffered router transforms message without making routing decision. Simulation results showed that S-mesh could get optimal performance in message latency compared with 2D-mesh, Butterfly and Octagon NoC architectures. The Design Compiler synthesis results showed that unbuffered router has obvious advantages on area, and it gets higher operation speed.