Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A switch architecture and signal synchronization for GALS system-on-chips
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
Evaluating SoC Network Performance in MPEG-4 Encoder
Journal of Signal Processing Systems
MPSoC architecture-aware automatic NoC topology design
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Abstract: The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most crucial factor to meet design constraints. This work goal is to define and implement algorithms devoted to analyze and select those communication architectures that better match the user defined system constraints, in an integrated design environment.