Digital systems engineering
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wave pipelining for application-specific networks-on-chips
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
High-Speed Clock Network Design
High-Speed Clock Network Design
Clocking strategies for networks-on-chip
Networks on chip
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Improving a fault-tolerant routing algorithm using detailed traffic analysis
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
| Hi-index | 0.01 |
One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution.In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between the switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case.The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.