Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Bounds on Maximum Delay in Networks with Deflection Routing
IEEE Transactions on Parallel and Distributed Systems
Deterministic Many-to-Many Hot Potato Routing
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Traffic Configuration for Evaluating Networks on Chips
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Fault-tolerant architecture and deflection routing for degradable NoC switches
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Proceedings of the Third International Workshop on Network on Chip Architectures
Switch allocator for bufferless network-on-chip routers
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Adaptive Flow Control for Robust Performance and Energy
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A NoC-based hybrid message-passing/shared-memory approach to CMP design
Microprocessors & Microsystems
Buffered deflection routing for networks-on-chip
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Exploring heterogeneous NoC design space
Proceedings of the International Conference on Computer-Aided Design
Making-a-stop: A new bufferless routing algorithm for on-chip network
Journal of Parallel and Distributed Computing
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
DeBAR: deflection based adaptive router with minimal buffering
Proceedings of the Conference on Design, Automation and Test in Europe
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Deflection routing is being proposed for networks on chips since it is simple and adaptive. A deflection switch can be much smaller and faster than a wormhole or virtual cut-through switch. A deflection-routed network has three orthogonal characteristics: topology, routing algorithm and deflection policy. In this paper we evaluate deflection networks with different topologies such as mesh, torus and Manhattan Street Network, different routing algorithms such as random, dimension XY, delta XY and minimum deflection, as well as different deflection policies such as non-priority, weighted priority and straight-through policies. Our results suggest that the performance of a deflection network is more sensitive to its topology than the other two parameters. It is less sensitive to its routing algorithm, but a routing algorithm should be minimal. A priority-based deflection policy that uses global and history-related criterion can achieve both better average-case and worst-case performance than a non-priority or priority policy that uses local and stateless criterion. These findings are important since they can guide designers to make right decisions on the deflection network architecture, for instance, selecting a routing algorithm or deflection policy which has potentially low cost and high speed for hardware implementation.