Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Router microarchitecture and scalability of ring topology in on-chip networks
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Buffer optimization in network-on-chip through flow regulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeBAR: deflection based adaptive router with minimal buffering
Proceedings of the Conference on Design, Automation and Test in Europe
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MPSoCs are becoming complex systems incorporating a large number of compute cores as well as various accelerators and application specific units. To handle the communication in MPSoCs, the Network-on-Chip (NoC) concept has been proposed as a versatile and scalable solution. The cost of the communication subsystem may have a major impact on the overall cost of the SoC; hence the need for careful evaluation of NoC design alternatives. Deflection routing, characterized by router simplicity and minimal resources, is an attractive design alternative but is generally viewed as suitable only for NoC with low and medium traffic. In this paper, we propose prioritization and buffering algorithms which improve deflection routing performance to the point it becomes attractive in heavily loaded NoC as well.