ACM Computing Surveys (CSUR)
IEEE Transactions on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the 34th annual international symposium on Computer architecture
On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
A low-latency modular switch for CMP systems
Microprocessors & Microsystems
Formally enhanced runtime verification to ensure NoC functional correctness
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Low power flitwise routing in an unidirectional torus with minimal buffering
Proceedings of the Fifth International Workshop on Network on Chip Architectures
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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On-chip networks are critical to the scaling of future multicore processors. Recent multicore processors have adopted ring topologies because of its simplicity and high bandwidth. In this paper, we first describe a bufferless router microarchitecture for an on-chip network ring topology. We propose to extend the bufferless router with an extra buffer entry to create a lightweight router microarchitecture. The proposed microarchitecture approaches ideal latency by reducing the microarchitecture complexity through minimizing the amount of buffers and simplifying switch allocation. We describe how the proposed lightweight microarchitecture does not need additional virtual channels to break routing deadlock. The scalability of the ring topology is presented as the network size increase. Although the ring topology has larger hop count with larger network diameter, lower per-hop router latency and no serialization latency results in lower latency for the ring topology compared to a 2D mesh topology. However, the wide channels in a ring topology creates bandwidth fragmentation which results in poor bandwidth utilization for short packets, compared to a 2D mesh topology, and can limit the scalability of the ring topology.