Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Router microarchitecture and scalability of ring topology in on-chip networks
Proceedings of the 2nd International Workshop on Network on Chip Architectures
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers
ECBS '10 Proceedings of the 2010 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging torus topology with deadlock recovery for cost-efficient on-chip network
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
RoShaQ: High-performance on-chip router with shared queues
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
| Hi-index | 0.00 |
State-of-the-art Network on Chips (NoCs) provide a high throughput and low latency by sending packets of data through a mesh topology, using virtual channels and wormhole flow control. The downside of this technology is a high area and energy consumption due to many buffers, large crossbars and a complex arbitration logic within the routers. In our approach, we avoid flow control and complex analysis of the head flit by sending single standalone flits instead of large packets of flits. As the order of flits is preserved between sending and receiving node, large data blocks can be sent anyway. The complexity of the router is further reduced by using an unidirectional 2D torus instead of a mesh, which reduces the number of router ports from 5 to 3. The flits are X-Y-routed and transported bufferless, as long as they stay within one dimension. Consequently there is only one FIFO per router, which buffers flits when they turn from X to Y direction. In terms of throughput and latency the so-called paternoster router is comparable with a conventional router with two virtual channels, but it consumes 50% less energy and 60% less area.