Low power flitwise routing in an unidirectional torus with minimal buffering
Proceedings of the Fifth International Workshop on Network on Chip Architectures
TM: a new and simple topology for interconnection networks
The Journal of Supercomputing
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On-chip networks are becoming more important as the number of on-chip components continue to increase. 2D mesh topology is a commonly assumed topology for on-chip networks but in this work, we make the argument that 2D torus can provide a more cost-efficient on-chip network since the on-chip network datapath is reduced by 2脳 while providing the same bisection bandwidth as a mesh network. Our results show that 2D torus can achieve an improvement of up to 1.9脳 over a 2D mesh in performance per watt metric. However, routing deadlock can occur in a torus network with the wrap-around channel and requires additional virtual channels for deadlock avoidance. In this work, we propose deadlock recovery with tokens (DRT) in on-chip networks that exploits on-chip networks - exploiting the abundant wires available while minimizing the need for additional buffers. As a result, deadlocks can be exactly detected without having to rely on a timeout mechanism and when needed, recover from the deadlock. We show how DRT results in minimal loss in performance, compared with deadlock avoidance using virtual channels, while reducing the on-chip network complexity.