On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing

Authors:
Tryggve Fossum
Affiliations:
INTEL Corporation
Venue:
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Year:
2007

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Abstract

There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling.